Risc-v isa extensions with hardware acceleration for hyperdimensional computing

Hyperdimensional Computing (HDC) offers a different way of processing information. Instead of relying on conventional numerical representations and computationally intensive neural architectures, it represents information through high-dimensional distributed vectors known as hypervectors. These representations can be manipulated through a small set of operations such as bundling, binding, permutation and similarity comparison, which can then be combined to perform learning tasks including classification, clustering and regression. The simplicity of these operations makes HDC particularly attractive for resource-constrained systems. However, executing them entirely in conventional software leaves part of their potential unexplored. High-dimensional vectors can contain thousands of elements, meaning that even conceptually simple operations must be repeated across large amounts of data. A different approach is therefore to bring these operations directly into the processor architecture, allowing the hardware itself to understand the computational language of HDC.

The solution extends the RISC-V Instruction Set Architecture with dedicated instructions specifically designed for Hyperdimensional Computing. Rather than translating every HDC operation into long sequences of conventional processor instructions, fundamental operations can be invoked directly at the ISA level. Dedicated instructions implement operations for bundling and binding hypervectors, permuting their elements, calculating similarity through Hamming distance, binarizing vectors and performing associative searches. Additional instructions manage transfers between main memory and specialized local memories. Importantly, this hardware specialization does not remove software programmability. The new instructions are integrated into the RISC-V GCC toolchain and exposed through intrinsic functions, allowing developers to access the accelerator from software without manually controlling every low-level hardware operation. The result is a bridge between a high-level HDC application and specialized hardware execution.

At the hardware level, the new instructions control a dedicated Hyperdimensional Coprocessor Unit (HDCU) integrated into the Klessydra-T03 RISC-V core. The architecture places the HDCU alongside the conventional Arithmetic Logic Unit and Load Store Unit during the processor’s execution stage. This means that the accelerator behaves as a specialized coprocessor rather than as an isolated external component. When an HDC instruction is encountered, the processor can delegate the corresponding operation to the appropriate hardware unit, while lightweight multithreading helps distribute workloads efficiently. Parallelism is central to the design. The HDCU uses a SIMD approach in which many elements of a hypervector can be processed simultaneously. A configuration with a SIMD width of 256, for example, can operate on 256 hypervector elements in parallel during a single cycle. Dedicated scratchpad memories further provide high-bandwidth, low-latency access to hypervectors, while hardware loops reduce the need to repeatedly fetch instructions when processing long vectors.

Specialized acceleration often creates a trade-off: greater performance can come at the cost of flexibility. The HDCU addresses this problem through two complementary levels of configurability. At synthesis time, designers can select the amount of hardware parallelism, available memory and supported operations. A highly parallel configuration can maximize execution speed, while a smaller implementation can reduce hardware-resource consumption. At runtime, Control Status Registers allow characteristics such as hypervector size and the number of operations to be modified dynamically. The same accelerator can therefore adapt to different workloads without requiring a new hardware implementation. This makes the architecture relevant across a broad range of systems, from constrained edge devices to implementations where higher computational throughput is the main priority.

The architecture is synthesized and tested on a Xilinx Zynq UltraScale+ ZCU106 FPGA platform. Performance is evaluated by comparing the number of processor cycles required by standard C implementations with those required when the same HDC operations are executed through dedicated hardware. The results show how strongly parallelism affects performance. Increasing the SIMD width progressively increases resource utilization but also produces dramatic acceleration. With hypervectors containing 8192 elements and a SIMD width of 1024 bits, individual HDC operations reached speedups of up to approximately 2665× compared with their software execution. The advantage is also tested beyond isolated arithmetic operations. In complete classification pipelines, including encoding, training and inference, the accelerator substantially reduces execution time. During inference, speedups reache approximately 297× on the CARDIO dataset and 2438× on the EMG dataset. These results demonstrate that the acceleration is not limited to synthetic processor benchmarks: it remains significant when HDC is used as an actual learning system.

The broader idea is to reconsider where intelligent computation should happen. Instead of treating the processor as a generic machine that executes every emerging AI paradigm through conventional instructions, the instruction set and microarchitecture can evolve together with new computational models. HDC is particularly suited to this direction because its fundamental operations are simple, highly parallel and naturally compatible with specialized digital hardware. By extending RISC-V with a native HDC instruction set and coupling it with a configurable accelerator, high-dimensional learning operations can move from software routines to direct hardware execution while remaining accessible to programmers. The result is not simply a faster implementation of HDC. It is an example of hardware-software co-design in which the processor itself becomes aware of the computational paradigm it is executing. This combination of programmability, configurable parallelism and domain-specific acceleration points toward a new generation of computing platforms capable of bringing efficient learning closer to the edge, where performance, energy efficiency and limited hardware resources must coexist.